TY - GEN
T1 - Hardware emulation of Memristor based Ternary Content Addressable Memory
AU - Bahloul, Mohamed
AU - Naous, Rawan
AU - Masmoudi, M.
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2017/12/13
Y1 - 2017/12/13
N2 - MTCAM (Memristor Ternary Content Addressable Memory) is a special purpose storage medium in which data could be retrieved based on the stored content. Using Memristors as the main storage element provides the potential of achieving higher density and more efficient solutions than conventional methods. A key missing item in the validation of such approaches is the wide spread availability of hardware emulation platforms that can provide reliable and repeatable performance statistics. In this paper, we present a hardware MTCAM emulation based on 2-Transistors-2Memristors (2T2M) bit-cell. It builds on a bipolar memristor model with storing and fetching capabilities based on the actual current-voltage behaviour. The proposed design offers a flexible verification environment with quick design revisions, high execution speeds and powerful debugging techniques. The proposed design is modeled using VHDL and prototyped on Xilinx Virtex® FPGA.
AB - MTCAM (Memristor Ternary Content Addressable Memory) is a special purpose storage medium in which data could be retrieved based on the stored content. Using Memristors as the main storage element provides the potential of achieving higher density and more efficient solutions than conventional methods. A key missing item in the validation of such approaches is the wide spread availability of hardware emulation platforms that can provide reliable and repeatable performance statistics. In this paper, we present a hardware MTCAM emulation based on 2-Transistors-2Memristors (2T2M) bit-cell. It builds on a bipolar memristor model with storing and fetching capabilities based on the actual current-voltage behaviour. The proposed design offers a flexible verification environment with quick design revisions, high execution speeds and powerful debugging techniques. The proposed design is modeled using VHDL and prototyped on Xilinx Virtex® FPGA.
UR - http://hdl.handle.net/10754/626429
UR - http://ieeexplore.ieee.org/document/8167029/
UR - http://www.scopus.com/inward/record.url?scp=85046626363&partnerID=8YFLogxK
U2 - 10.1109/SSD.2017.8167029
DO - 10.1109/SSD.2017.8167029
M3 - Conference contribution
SN - 9781538631751
SP - 446
EP - 449
BT - 2017 14th International Multi-Conference on Systems, Signals & Devices (SSD)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -