TY - GEN

T1 - Hierarchical Parallel Matrix Multiplication on Large-Scale Distributed Memory Platforms

AU - Quintin, Jean-Noel

AU - Hasanov, Khalid

AU - Lastovetsky, Alexey

N1 - KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: The research in this paper was supported by IRCSET(IrishResearch Council for Science, Engineering and Technol-ogy) and IBM, grant numbers EPSG/2011/188 and EP-SPD/2011/207.Some of the experiments presented in this paper werecarried out using the Grid’5000 experimental testbed, beingdeveloped under the INRIA ALADDIN development actionwith support from CNRS, RENATER and several Universitiesas well as other funding bodies (see https://www.grid5000.fr)Another part of the experiments in this research were carriedout using the resources of the Supercomputing Laboratory atKing Abdullah University of Science&Technology (KAUST)in Thuwal, Saudi Arabia.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.

PY - 2013/10

Y1 - 2013/10

N2 - Matrix multiplication is a very important computation kernel both in its own right as a building block of many scientific applications and as a popular representative for other scientific applications. Cannon's algorithm which dates back to 1969 was the first efficient algorithm for parallel matrix multiplication providing theoretically optimal communication cost. However this algorithm requires a square number of processors. In the mid-1990s, the SUMMA algorithm was introduced. SUMMA overcomes the shortcomings of Cannon's algorithm as it can be used on a nonsquare number of processors as well. Since then the number of processors in HPC platforms has increased by two orders of magnitude making the contribution of communication in the overall execution time more significant. Therefore, the state of the art parallel matrix multiplication algorithms should be revisited to reduce the communication cost further. This paper introduces a new parallel matrix multiplication algorithm, Hierarchical SUMMA (HSUMMA), which is a redesign of SUMMA. Our algorithm reduces the communication cost of SUMMA by introducing a two-level virtual hierarchy into the two-dimensional arrangement of processors. Experiments on an IBM BlueGene/P demonstrate the reduction of communication cost up to 2.08 times on 2048 cores and up to 5.89 times on 16384 cores. © 2013 IEEE.

AB - Matrix multiplication is a very important computation kernel both in its own right as a building block of many scientific applications and as a popular representative for other scientific applications. Cannon's algorithm which dates back to 1969 was the first efficient algorithm for parallel matrix multiplication providing theoretically optimal communication cost. However this algorithm requires a square number of processors. In the mid-1990s, the SUMMA algorithm was introduced. SUMMA overcomes the shortcomings of Cannon's algorithm as it can be used on a nonsquare number of processors as well. Since then the number of processors in HPC platforms has increased by two orders of magnitude making the contribution of communication in the overall execution time more significant. Therefore, the state of the art parallel matrix multiplication algorithms should be revisited to reduce the communication cost further. This paper introduces a new parallel matrix multiplication algorithm, Hierarchical SUMMA (HSUMMA), which is a redesign of SUMMA. Our algorithm reduces the communication cost of SUMMA by introducing a two-level virtual hierarchy into the two-dimensional arrangement of processors. Experiments on an IBM BlueGene/P demonstrate the reduction of communication cost up to 2.08 times on 2048 cores and up to 5.89 times on 16384 cores. © 2013 IEEE.

UR - http://hdl.handle.net/10754/598457

UR - http://ieeexplore.ieee.org/document/6687414/

UR - http://www.scopus.com/inward/record.url?scp=84893326980&partnerID=8YFLogxK

U2 - 10.1109/ICPP.2013.89

DO - 10.1109/ICPP.2013.89

M3 - Conference contribution

SN - 9780769551173

SP - 754

EP - 762

BT - 2013 42nd International Conference on Parallel Processing

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -