TY - JOUR
T1 - High-performance silicon nanotube tunneling FET for ultralow-power logic applications
AU - Fahad, Hossain M.
AU - Hussain, Muhammad Mustafa
N1 - KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: This work was supported by the Office of Sponsored Research at King Abdullah University of Science and Technology under Competitive Research Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor W. Tsai.
PY - 2013/3
Y1 - 2013/3
N2 - To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
AB - To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
UR - http://hdl.handle.net/10754/562674
UR - http://ieeexplore.ieee.org/document/6463442/
UR - http://www.scopus.com/inward/record.url?scp=84874662371&partnerID=8YFLogxK
U2 - 10.1109/TED.2013.2243151
DO - 10.1109/TED.2013.2243151
M3 - Article
SN - 0018-9383
VL - 60
SP - 1034
EP - 1039
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 3
ER -