High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

Chenhsin Lien; Hao-Ling Tang; Ming-Hui Chiu; Kuan-Jhih Hou; Shih-Hsien Yang; Jhih-Fong Su; Yen-Fu Lin; Lain-Jong Li

doi:10.1109/ICSICT.2018.8565030

High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

Chenhsin Lien, Hao-Ling Tang, Ming-Hui Chiu, Kuan-Jhih Hou, Shih-Hsien Yang, Jhih-Fong Su, Yen-Fu Lin, Lain-Jong Li

Physical Sciences and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

P-channel WSe2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe2 served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the Ion/Ioff ratio can be enhanced to 108 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.

Original language	English (US)
Title of host publication	2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Print)	9781538644409
DOIs	https://doi.org/10.1109/ICSICT.2018.8565030
State	Published - Oct 2018

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10.1109/ICSICT.2018.8565030

https://repository.kaust.edu.sa/bitstream/10754/655977/1/08565030.pdf

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Lien, C., Tang, H.-L., Chiu, M.-H., Hou, K.-J., Yang, S.-H., Su, J.-F., Lin, Y.-F., & Li, L.-J. (2018). High Performance WSe2 Transistors with Multilayer Graphene Source/Drain. In 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ICSICT.2018.8565030

@inproceedings{bd6dc7a070fc459c9aef9d40046d6647,

title = "High Performance WSe2 Transistors with Multilayer Graphene Source/Drain",

abstract = "P-channel WSe2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe2 served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the Ion/Ioff ratio can be enhanced to 108 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.",

author = "Chenhsin Lien and Hao-Ling Tang and Ming-Hui Chiu and Kuan-Jhih Hou and Shih-Hsien Yang and Jhih-Fong Su and Yen-Fu Lin and Lain-Jong Li",

note = "KAUST Repository Item: Exported on 2020-10-01",

year = "2018",

month = oct,

doi = "10.1109/ICSICT.2018.8565030",

language = "English (US)",

isbn = "9781538644409",

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High Performance WSe2 Transistors with Multilayer Graphene Source/Drain. / Lien, Chenhsin; Tang, Hao-Ling; Chiu, Ming-Hui et al.
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). Institute of Electrical and Electronics Engineers (IEEE), 2018.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

AU - Lien, Chenhsin

AU - Tang, Hao-Ling

AU - Chiu, Ming-Hui

AU - Hou, Kuan-Jhih

AU - Yang, Shih-Hsien

AU - Su, Jhih-Fong

AU - Lin, Yen-Fu

AU - Li, Lain-Jong

N1 - KAUST Repository Item: Exported on 2020-10-01

PY - 2018/10

Y1 - 2018/10

N2 - P-channel WSe2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe2 served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the Ion/Ioff ratio can be enhanced to 108 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.

AB - P-channel WSe2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe2 served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the Ion/Ioff ratio can be enhanced to 108 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.

UR - http://hdl.handle.net/10754/655977

UR - https://ieeexplore.ieee.org/document/8565030/

UR - http://www.scopus.com/inward/record.url?scp=85060285656&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2018.8565030

DO - 10.1109/ICSICT.2018.8565030

M3 - Conference contribution

SN - 9781538644409

BT - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

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