High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

Chenhsin Lien, Hao-Ling Tang, Ming-Hui Chiu, Kuan-Jhih Hou, Shih-Hsien Yang, Jhih-Fong Su, Yen-Fu Lin, Lain-Jong Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution


P-channel WSe2 FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe2 monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe2 served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the Ion/Ioff ratio can be enhanced to 108 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.
Original languageEnglish (US)
Title of host publication2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Print)9781538644409
StatePublished - Oct 2018


Dive into the research topics of 'High Performance WSe2 Transistors with Multilayer Graphene Source/Drain'. Together they form a unique fingerprint.

Cite this