TY - JOUR
T1 - Implementation of low EMI spread spectrum clock generators exploiting a chaos-based jitter
AU - Pareschi, Fabio
AU - Setti, Gianluca
AU - Callegari, Sergio
AU - Rovatti, Riccardo
N1 - Generated from Scopus record by KAUST IRTS on 2023-02-15
PY - 2009/2/16
Y1 - 2009/2/16
N2 - We show how the ability to design chaotic circuits with prescribed statistical features is fundamental for the reduction of Electromagnetic Interference (EMI) due to timing signals, such as the clock signals widely employed in digital circuits. In fact, due to their periodic nature and to the presence of sharp edges, the power of such signals is concentrated at those frequencies corresponding to the multiples of the timing signal period. This can obviously produce serious concerns in terms of EMI. For simple clock signals, an appreciable EMI reduction can be achieved by means of a simple quasi-stationary frequency modulation (FM) directed at intentionally perturbing a normally narrowband signal, thus spreading the energy associate to each harmonic over a large bandwidth in order to reduce the peak value. More specifically here we review some different solutions to show that modulations which employ a random signal are the most suitable for EMI reduction. Furthermore, we present some analytic expressions linking the power density spectrum of a FM timing signal to the features of the modulation a PAM signal generated by a one-dimensional chaotic map, both in the case of slow (quasi-stationary) modulation and for the opposite case of fast-modulation. We also show how the case of fast modulation offers further advantages with respect to slow modulation, in terms of EMI reduction. Theoretical results are also compared with measurement from two different prototypes of low EMI Spread Spectrum Clock Generators (SSCGs) in CMOS technology which employ a fast modulation. The first one is designed in an established technology, and a low frequency (f0 = 100MHz) has been chosen because considered suitable for proving the obtained theoretical results. The second one is the scaling of the first to a more advanced technology, and it has been designed in order to operate at a much higher frequency, namely f0 = 2.5GHz. The EMI reduction, for the two prototypes, has been measured respectively in 18 dB and 16 dB. In both prototype the random modulating signal is given by the output of an ADC-based Random Bit Generator, obtained through a chaotic map, which is described in details in chapter 8. © 2009 Springer-Verlag Berlin Heidelberg.
AB - We show how the ability to design chaotic circuits with prescribed statistical features is fundamental for the reduction of Electromagnetic Interference (EMI) due to timing signals, such as the clock signals widely employed in digital circuits. In fact, due to their periodic nature and to the presence of sharp edges, the power of such signals is concentrated at those frequencies corresponding to the multiples of the timing signal period. This can obviously produce serious concerns in terms of EMI. For simple clock signals, an appreciable EMI reduction can be achieved by means of a simple quasi-stationary frequency modulation (FM) directed at intentionally perturbing a normally narrowband signal, thus spreading the energy associate to each harmonic over a large bandwidth in order to reduce the peak value. More specifically here we review some different solutions to show that modulations which employ a random signal are the most suitable for EMI reduction. Furthermore, we present some analytic expressions linking the power density spectrum of a FM timing signal to the features of the modulation a PAM signal generated by a one-dimensional chaotic map, both in the case of slow (quasi-stationary) modulation and for the opposite case of fast-modulation. We also show how the case of fast modulation offers further advantages with respect to slow modulation, in terms of EMI reduction. Theoretical results are also compared with measurement from two different prototypes of low EMI Spread Spectrum Clock Generators (SSCGs) in CMOS technology which employ a fast modulation. The first one is designed in an established technology, and a low frequency (f0 = 100MHz) has been chosen because considered suitable for proving the obtained theoretical results. The second one is the scaling of the first to a more advanced technology, and it has been designed in order to operate at a much higher frequency, namely f0 = 2.5GHz. The EMI reduction, for the two prototypes, has been measured respectively in 18 dB and 16 dB. In both prototype the random modulating signal is given by the output of an ADC-based Random Bit Generator, obtained through a chaotic map, which is described in details in chapter 8. © 2009 Springer-Verlag Berlin Heidelberg.
UR - http://link.springer.com/10.1007/978-3-540-95972-4_7
UR - http://www.scopus.com/inward/record.url?scp=59849094248&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-95972-4_7
DO - 10.1007/978-3-540-95972-4_7
M3 - Article
SN - 1860-949X
VL - 184
SP - 145
EP - 171
JO - Studies in Computational Intelligence
JF - Studies in Computational Intelligence
ER -