TY - GEN
T1 - Improved circuit model for all-spin logic
AU - Alawein, Meshal
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2021-09-14
PY - 2016/9/15
Y1 - 2016/9/15
N2 - Spintronic devices are prime candidates for Beyond CMOS era due to their potential for low power consumption and high density computation and storage. All-spin logic (ASL) is among the most promising spintronic logic switches. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of the transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect (SHE) and spin-orbit torque (SOT). In this paper, and based on a finite difference scheme, we propose an improved self-consisting magnetization dynamics/time-dependent carrier transport model that captures the main characteristics of ASL devices.
AB - Spintronic devices are prime candidates for Beyond CMOS era due to their potential for low power consumption and high density computation and storage. All-spin logic (ASL) is among the most promising spintronic logic switches. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of the transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect (SHE) and spin-orbit torque (SOT). In this paper, and based on a finite difference scheme, we propose an improved self-consisting magnetization dynamics/time-dependent carrier transport model that captures the main characteristics of ASL devices.
UR - http://hdl.handle.net/10754/656026
UR - https://ieeexplore.ieee.org/document/7568640/
UR - http://www.scopus.com/inward/record.url?scp=84992147487&partnerID=8YFLogxK
U2 - 10.1145/2950067.2950075
DO - 10.1145/2950067.2950075
M3 - Conference contribution
AN - SCOPUS:84992147487
SN - 9781450343305
SP - 135
EP - 140
BT - 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -