Improved interface characterization technique for high-k/metal gated MugFETs utilizing a gated diode structure

As CMOS trends continue to scale for future technology nodes, three-dimensional (3D) multi-gate field effect transistors (MugFETs) could be a viable approach. One type of MugGET of particular interest is the FinFET in which a silicon fin is defined on a buried oxide (BOX) layer. The FinFET is attractive because it is compatible with conventional CMOS processing. However, due to the crystal orientation of the fin sidewalls, their interface with the gate dielectric may contain more interface states, as well as be more sensitive to stress-induced degradation than planar devices. Therefore, these interface states and their impact on longterm operation must be characterized. FinFETs on BOX, however, do not have a substrate contact for traditional interface state characterization methods. To circumvent this issue, a gated diode FinFET test structure can be used, which emulates a planar device configuration allowing interface characterization techniques such as charge pumping (CP) [1, 2] and DC gated-diode current-voltage (DCIV) measurements [3, 4]. To determine which technique best characterizes sidewall interfaces; CP and DCIV measurements were used to monitor the time evolution of interface state generation and oxide charging during bias temperature instability (BTI) tests of the gated diode FinFETs.