Improving effective yield through error tolerant system design

Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/ICECS.2005.4633574

Improving effective yield through error tolerant system design

Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.

Original language	English (US)
Title of host publication	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
DOIs	https://doi.org/10.1109/ICECS.2005.4633574
State	Published - Dec 1 2005
Externally published	Yes

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10.1109/ICECS.2005.4633574

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title = "Improving effective yield through error tolerant system design",

abstract = "This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.",

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N2 - This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.

AB - This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.

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M3 - Conference contribution

SN - 9789972611001

BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

ER -

Improving effective yield through error tolerant system design

Abstract

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