Abstract
A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the subthreshold swing, and the intrinsic time delay, etc. The drive current of the in-line TFET is enhanced nearly 7× compared to the conventional TFET. It also shows a significantly reduced subthreshold swing of 37.2 mV/dec.
Original language | English (US) |
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Pages (from-to) | 721-725 |
Number of pages | 5 |
Journal | IEEE Journal of the Electron Devices Society |
Volume | 6 |
DOIs | |
State | Published - Jun 4 2018 |
Keywords
- TFET
- in-line tunneling
- silicon
- tunneling distance
- tunneling probability
- vertical structure
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
- Biotechnology