Initiation Interval Aware Resource Sharing for FPGA DSP Blocks

Ronak Bajaj; Suhaib A. Fahmy

doi:10.1109/FCCM.2016.40

Initiation Interval Aware Resource Sharing for FPGA DSP Blocks

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Resource sharing attempts to minimise usage of hardware blocks by mapping multiple operations onto same block at the cost of an increase in schedule length and initiation interval (II). Sharing multi-cycle high-throughput DSP blocks using traditional approaches results in significantly high II, determined by structure of dataflow graph of the design, thus limiting achievable throughput. We have developed a resource sharing technique that minimises the number of DSP blocks and schedule length given an II constraint.

Original language	English (US)
Title of host publication	Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781509023561
DOIs	https://doi.org/10.1109/FCCM.2016.40
State	Published - Aug 16 2016
Externally published	Yes

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10.1109/FCCM.2016.40

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AB - Resource sharing attempts to minimise usage of hardware blocks by mapping multiple operations onto same block at the cost of an increase in schedule length and initiation interval (II). Sharing multi-cycle high-throughput DSP blocks using traditional approaches results in significantly high II, determined by structure of dataflow graph of the design, thus limiting achievable throughput. We have developed a resource sharing technique that minimises the number of DSP blocks and schedule length given an II constraint.

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BT - Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Initiation Interval Aware Resource Sharing for FPGA DSP Blocks

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