Iterative floating point computation using FPGA DSP blocks

This paper presents a single precision floating point unit design for multiplication and addition/subtraction using FPGA DSP blocks. The design is based around the DSP48E1 primitive found in Virtex-6 and all 7-series FPGAs from Xilinx. Since the DSP48E1 can be dynamically configured and used for many of the sub-operations involved in IEEE 754-2008 binary32 floating point multiplication and addition, we demonstrate an iterative combined operator that uses a single DSP block and minimal logic. Logic-only and fixed-configuration DSP block designs, and other state-of-the-art implementations, including the Xilinx CoreGen operators are compared to this approach. Since FPGA based systems typically run at a fraction of the maximum possible FPGA speed, and in some cases, floating point computations may not be required in every cycle, the iterative approach represents an efficient way to leverage DSP resources for what can otherwise be costly operations. © 2013 IEEE.