La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

C. S. Park; J. W. Yang; M. M. Hussain; C. Y. Kang; J. Huang; P. Sivasubramani; C. Park; K. Tateiwa; Y. Harada; J. Barnett; C. Melvin; G. Bersuker; P. D. Kirsch; B. H. Lee; H. H. Tseng; R. Jammy

doi:10.1109/VTSA.2009.5159290

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

C. S. Park, J. W. Yang, M. M. Hussain, C. Y. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. D. Kirsch, B. H. Lee, H. H. Tseng, R. Jammy

Computer, Electrical and Mathematical Sciences and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent I_on-I_off characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, V_t variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses V_t variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

Original language	English (US)
Title of host publication	2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
Pages	59-60
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2009.5159290
State	Published - 2009
Event	2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 - Hsinchu, Taiwan, Province of China Duration: Apr 27 2009 → Apr 29 2009

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Other

Other	2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	04/27/09 → 04/29/09

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/VTSA.2009.5159290

Cite this

Park, C. S., Yang, J. W., Hussain, M. M., Kang, C. Y., Huang, J., Sivasubramani, P., Park, C., Tateiwa, K., Harada, Y., Barnett, J., Melvin, C., Bersuker, G., Kirsch, P. D., Lee, B. H., Tseng, H. H., & Jammy, R. (2009). La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application. In 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 (pp. 59-60). Article 5159290 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2009.5159290

@inproceedings{1c66144f6dca44d3b4e73d0647453abd,

title = "La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application",

abstract = "This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.",

author = "Park, {C. S.} and Yang, {J. W.} and Hussain, {M. M.} and Kang, {C. Y.} and J. Huang and P. Sivasubramani and C. Park and K. Tateiwa and Y. Harada and J. Barnett and C. Melvin and G. Bersuker and Kirsch, {P. D.} and Lee, {B. H.} and Tseng, {H. H.} and R. Jammy",

year = "2009",

doi = "10.1109/VTSA.2009.5159290",

language = "English (US)",

isbn = "9781424427857",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

pages = "59--60",

booktitle = "2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09",

note = "2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09 ; Conference date: 27-04-2009 Through 29-04-2009",

}

Park, CS, Yang, JW, Hussain, MM, Kang, CY, Huang, J, Sivasubramani, P, Park, C, Tateiwa, K, Harada, Y, Barnett, J, Melvin, C, Bersuker, G, Kirsch, PD, Lee, BH, Tseng, HH & Jammy, R 2009, La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application. in 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09., 5159290, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, pp. 59-60, 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09, Hsinchu, Taiwan, Province of China, 04/27/09. https://doi.org/10.1109/VTSA.2009.5159290

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application. / Park, C. S.; Yang, J. W.; Hussain, M. M. et al.
2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09. 2009. p. 59-60 5159290 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

AU - Park, C. S.

AU - Yang, J. W.

AU - Hussain, M. M.

AU - Kang, C. Y.

AU - Huang, J.

AU - Sivasubramani, P.

AU - Park, C.

AU - Tateiwa, K.

AU - Harada, Y.

AU - Barnett, J.

AU - Melvin, C.

AU - Bersuker, G.

AU - Kirsch, P. D.

AU - Lee, B. H.

AU - Tseng, H. H.

AU - Jammy, R.

PY - 2009

Y1 - 2009

N2 - This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

AB - This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

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U2 - 10.1109/VTSA.2009.5159290

DO - 10.1109/VTSA.2009.5159290

M3 - Conference contribution

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SN - 9781424427857

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SP - 59

EP - 60

BT - 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09

T2 - 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09

Y2 - 27 April 2009 through 29 April 2009

ER -

Park CS, Yang JW, Hussain MM, Kang CY, Huang J, Sivasubramani P et al. La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application. In 2009 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA '09. 2009. p. 59-60. 5159290. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). doi: 10.1109/VTSA.2009.5159290

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

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