Layout Techniques for Minimizing On-Chip Interconnect Self Inductance

Yehia Massoud, Steve Majors, Tareq Bustami, Jacob White

Research output: Chapter in Book/Report/Conference proceedingConference contribution

89 Scopus citations


Because magnetic effects have a much longer spatial range than electrostatic effects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it difficult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two- And threedimensional electromagnetic field solvers to compare dedicated ground planes to a less area-consuming approach, interdigitating the signal line with ground lines. The surprising conclusion is that with very little area penalty, interdigitated ground lines are more effective at minimizing self-inductance than ground planes.
Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)078034409X
StatePublished - Jan 1 1998
Externally publishedYes


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