TY - GEN
T1 - Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design
T2 - 35th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024
AU - Bouaziz, Mohamed
AU - Fahmy, Suhaib A.
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Coarse-grained reconfigurable arrays (CGRAs) are reconfigurable architectures that combine the efficiency of custom datapaths with the flexibility of FPGAs. Optimized word-level functional units with reconfigurable interconnect enable a wide range of applications. Due to the irregular data movement patterns and the diversity of real-world HPC applications, a traditional homogeneous regular-shaped CGRA architecture can be sub-optimal. A more application-specific arrangement of resources could, however, result in poor hardware reuse and increased deployment effort for a CGRA. Using CGRA overlays can increase hardware reuse while maintaining high performance of a more optimized architecture. This proposal uses and builds upon the built-in tools of the MLIR infrastructure to target a class of applications that can be analyzed, rewritten, and optimized based on the available resources of an underlying CGRA architecture, thereby better exploiting hardware resources.
AB - Coarse-grained reconfigurable arrays (CGRAs) are reconfigurable architectures that combine the efficiency of custom datapaths with the flexibility of FPGAs. Optimized word-level functional units with reconfigurable interconnect enable a wide range of applications. Due to the irregular data movement patterns and the diversity of real-world HPC applications, a traditional homogeneous regular-shaped CGRA architecture can be sub-optimal. A more application-specific arrangement of resources could, however, result in poor hardware reuse and increased deployment effort for a CGRA. Using CGRA overlays can increase hardware reuse while maintaining high performance of a more optimized architecture. This proposal uses and builds upon the built-in tools of the MLIR infrastructure to target a class of applications that can be analyzed, rewritten, and optimized based on the available resources of an underlying CGRA architecture, thereby better exploiting hardware resources.
UR - http://www.scopus.com/inward/record.url?scp=85203105651&partnerID=8YFLogxK
U2 - 10.1109/ASAP61560.2024.00048
DO - 10.1109/ASAP61560.2024.00048
M3 - Conference contribution
AN - SCOPUS:85203105651
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 204
EP - 205
BT - Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 24 July 2024 through 26 July 2024
ER -