TY - GEN
T1 - Limits on voltage scaling for caches utilizing fault tolerant techniques
AU - Makhzan, Mohammad A.
AU - Khajeh, Amin
AU - Eltawil, Ahmed
AU - Kurdahi, Fadi
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks. © 2007 IEEE.
AB - This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4601943/
UR - http://www.scopus.com/inward/record.url?scp=52949089661&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2007.4601943
DO - 10.1109/ICCD.2007.4601943
M3 - Conference contribution
SN - 1424412587
BT - 2007 IEEE International Conference on Computer Design, ICCD 2007
ER -