Low overhead correction scheme for unreliable LDPC buffering

Amr M.A. Hussien; Wael M. Elsharkasy; Ahmed M. Eltawil; Fadi Kurdahi; Amin Khajeh

doi:10.1109/GlobalSIP.2013.6736979

Low overhead correction scheme for unreliable LDPC buffering

Amr M.A. Hussien, Wael M. Elsharkasy, Ahmed M. Eltawil, Fadi Kurdahi, Amin Khajeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%. © 2013 IEEE.

Original language	English (US)
Title of host publication	2013 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013 - Proceedings
DOIs	https://doi.org/10.1109/GlobalSIP.2013.6736979
State	Published - Dec 1 2013
Externally published	Yes

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10.1109/GlobalSIP.2013.6736979

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title = "Low overhead correction scheme for unreliable LDPC buffering",

abstract = "Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%. {\textcopyright} 2013 IEEE.",

author = "Hussien, {Amr M.A.} and Elsharkasy, {Wael M.} and Eltawil, {Ahmed M.} and Fadi Kurdahi and Amin Khajeh",

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doi = "10.1109/GlobalSIP.2013.6736979",

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AU - Hussien, Amr M.A.

AU - Elsharkasy, Wael M.

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi

AU - Khajeh, Amin

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2013/12/1

Y1 - 2013/12/1

N2 - Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%. © 2013 IEEE.

AB - Aggressive voltage overscaling (VOS) has been recently adopted to reduce the power consumption of embedded memories. While this affects reliability, several techniques have been developed to achieve reliable operation under aggressive VOS. In this paper, we present a comprehensive power-performance study of LDPC decoders enabling aggressive VOS to internal memories. We propose a correction scheme based on defect map insertion that maintains reliable LDPC decoder under aggressive VOS. The proposed scheme maintains the LDPC decoder performance while achieving a power saving of up to 21%. © 2013 IEEE.

UR - http://ieeexplore.ieee.org/document/6736979/

UR - http://www.scopus.com/inward/record.url?scp=84897732210&partnerID=8YFLogxK

U2 - 10.1109/GlobalSIP.2013.6736979

DO - 10.1109/GlobalSIP.2013.6736979

M3 - Conference contribution

SN - 9781479902484

BT - 2013 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013 - Proceedings

ER -

Low overhead correction scheme for unreliable LDPC buffering

Abstract

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