Low power reduced-complexity error-resilient MIMO detector

Chung An Shen; Muhammad S. Khairy; Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/ISCAS.2014.6865478

Low power reduced-complexity error-resilient MIMO detector

Chung An Shen, Muhammad S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are given showing that the circuit-level optimization decreases the detector area by 15% and power consumption by 41%. Moreover, we show that the proposed error-resilient MIMO detector with reduced-voltage memory can achieve a total of 19% reduction in power consumption compared with the conventional scheme, while still maintaining close-to optimal PER performance. © 2014 IEEE.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865478
State	Published - Jan 1 2014
Externally published	Yes

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10.1109/ISCAS.2014.6865478

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title = "Low power reduced-complexity error-resilient MIMO detector",

abstract = "This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are given showing that the circuit-level optimization decreases the detector area by 15% and power consumption by 41%. Moreover, we show that the proposed error-resilient MIMO detector with reduced-voltage memory can achieve a total of 19% reduction in power consumption compared with the conventional scheme, while still maintaining close-to optimal PER performance. {\textcopyright} 2014 IEEE.",

author = "Shen, {Chung An} and Khairy, {Muhammad S.} and Eltawil, {Ahmed M.} and Kurdahi, {Fadi J.}",

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doi = "10.1109/ISCAS.2014.6865478",

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T1 - Low power reduced-complexity error-resilient MIMO detector

AU - Shen, Chung An

AU - Khairy, Muhammad S.

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi J.

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are given showing that the circuit-level optimization decreases the detector area by 15% and power consumption by 41%. Moreover, we show that the proposed error-resilient MIMO detector with reduced-voltage memory can achieve a total of 19% reduction in power consumption compared with the conventional scheme, while still maintaining close-to optimal PER performance. © 2014 IEEE.

AB - This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are given showing that the circuit-level optimization decreases the detector area by 15% and power consumption by 41%. Moreover, we show that the proposed error-resilient MIMO detector with reduced-voltage memory can achieve a total of 19% reduction in power consumption compared with the conventional scheme, while still maintaining close-to optimal PER performance. © 2014 IEEE.

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U2 - 10.1109/ISCAS.2014.6865478

DO - 10.1109/ISCAS.2014.6865478

M3 - Conference contribution

SN - 9781479934324

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Low power reduced-complexity error-resilient MIMO detector

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