Low-Power Resistive Associative Processor Implementation Through the Multi-Compare

Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


The computation based on traditional architectures is approaching its limits in terms of scalability and energy consumption. The main issue contributing to this fact is memory bottleneck. To overcome this issue, the most promising methodology is parallelism where multiple cores are utilized to perform concurrent operations on their local memories. The ultimate processor architecture in this trend is associative processors where each row in the memory behaves as a single core. With the advent of emerging memory technologies such as Resisitve RAMs (and in particular, memristors), lower footprint and high-performance associative processors became possible. On the other hand, the high write energy of the memristors poses a significant reliability thread for the applicability. This study aims to overcome this problem by wisely managing the trade-off between the memristor write energy and the memristance scaling. To preserve the accuracy affected by the scaling, the study proposes a multi-cycle compare scheme. Results on seven different benchmarks report an average 1.12x speedup with a 54.16x improvement in the energy consumption.
Original languageEnglish (US)
Title of host publication2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781538695623
StatePublished - Jan 17 2019
Externally publishedYes


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