Abstract
Reducing wafer thickness while increasing power conversion efficiency is the most effective way to reduce cost per Watt of a silicon photovoltaic module. Within the European project 20 percent efficiency on less than 100-μm-thick, industrially feasible crystalline silicon solar cells ("20plms"), we study the whole process chain for thin wafers, from wafering to module integration and life-cycle analysis. We investigate three different solar cell fabrication routes, categorized according to the temperature of the junction formation process and the wafer doping type: p-type silicon high temperature, n-type silicon high temperature and n-type silicon low temperature. For each route, an efficiency of 19.5% or greater is achieved on wafers less than 100 μm thick, with a maximum efficiency of 21.1% on an 80-μm-thick wafer. The n-type high temperature route is then transferred to a pilot production line, and a median solar cell efficiency of 20.0% is demonstrated on 100-μm-thick wafers.
Original language | English (US) |
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Pages (from-to) | 13-24 |
Number of pages | 12 |
Journal | Physica Status Solidi (A) Applications and Materials Science |
Volume | 212 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2015 |
Externally published | Yes |
Keywords
- High efficiency
- Pilot production
- Silicon
- Solar cells
- Thin wafers
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Surfaces and Interfaces
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering
- Materials Chemistry