Memristive non-idealities: Is there any practical implications for designing neural network chips?

Olga Krestinskaya, Aidana Irmanova, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

The impact of device-to-device, cycle-to-cycle, and parasitic variations in memristor devices on the performance of neural network architectures is not a fully understood topic. In this paper, we present an explicit analysis of memristor variabilities and non-idealities of memristive crossbar based learning architectures. The measurements of real devices and their effects on dot product operation in a memristive crossbar is reported. The effect of these non-idealities, limited resistive levels and variabilities on the performance and reliability of two-layer Artificial Neural Network (ANN), Convolutional Neural Network (CNN) and Binary Neural Network (BNN) is analyzed and presented.
Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781728103976
DOIs
StatePublished - Jan 1 2019
Externally publishedYes

Fingerprint

Dive into the research topics of 'Memristive non-idealities: Is there any practical implications for designing neural network chips?'. Together they form a unique fingerprint.

Cite this