Monolithic 3D CMOS Using Layered Semiconductors

Angada B. Sachid, Mahmut Tosun, Sujay B. Desai, Ching-Yi Hsu, Der-Hsien Lien, Surabhi R. Madhvapathy, Yu-Ze Chen, Mark Hettick, Jeong Seuk Kang, Yuping Zeng, Jr-Hau He, Edward Yi Chang, Yu-Lun Chueh, Ali Javey, Chenming Hu

Research output: Contribution to journalArticlepeer-review

108 Scopus citations


Monolithic 3D integration of high performance MoS2 and WSe2 layered semiconductor metal oxide semiconductor field effect transistors (MOSFETs) with electron and hole mobility of 38 and 238 cm2 were reported. To calculate the circuit area, layouts were designed for single-layer (1 layer) and monolithic 3D (2 layer) CMOS using design rules for the 14 nm technology node. To fabricate the first layer MOSFET, MoS2 thin flakes are exfoliated on to Si/SiO2 substrate. Flakes with appropriate thicknesses are etched into rectangular patterns using xenon difluoride followed by source/drain, gate oxide, and metal gate formation. Thick layers of SiOx and ZrO2 are deposited on top of the bottom layer MoS2 transistors to reduce the interlayer capacitive coupling between bottom and top layer devices followed by MoS2 dry transfer and etch. The interlayer capacitance is inversely proportional to the oxide thickness between the top and bottom layer transistors and increasing the oxide thickness decreases the interlayer capacitance. This low-temperature, monolithic 3D integration platform can potentially enable highly integrated and massively interconnected computing platforms with ultralow energy consumption such as neuromorphic computing.
Original languageEnglish (US)
Pages (from-to)2547-2554
Number of pages8
JournalAdvanced Materials
Issue number13
StatePublished - Feb 2 2016


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