Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration

Alex R. Bucknall, Shanker Shreejith, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter often makes use of the PCIe interface and supporting infrastructure to allocate and load compute kernels via a host CPU, FPGAs are becoming increasingly popular as standalone resources in edge-computing, requiring them to manage accelerators autonomously. This paper presents a platform that supports the managing of accelerator bitstreams over the network interface on a Xilinx Zynq device without intervention by the Arm processor. We compare against traditional vendor provided PR management for both library accelerators and custom accelerators and show that we achieve a 29% decrease in reconfiguration trigger latency using this approach.
Original languageEnglish (US)
Title of host publicationProceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781728129433
StatePublished - Dec 1 2019
Externally publishedYes


Dive into the research topics of 'Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration'. Together they form a unique fingerprint.

Cite this