We can design high-frequency soft-processors on FPGAs that exploit deep pipelining of DSP primitives, supported by selective data forwarding, to deliver up to 25% performance improvements across a range of benchmarks. Pipelined, inorder, scalar processors can be small and lightweight but suffer from a large number of idle cycles due to dependency chains in the instruction sequence. Data forwarding allows us to more deeply pipeline the processor stages while avoiding an associated increase in the NOP cycles between dependent instructions. Full forwarding can be prohibitively complex for a lean soft processor, so we explore two approaches: an external forwarding path around the DSP block execution unit in FPGA logic and using the intrinsic loopback path within the DSP block primitive. We show that internal loopback improves performance by 5% compared to external forwarding, and up to 25% over no data forwarding. The result is a processor that runs at a frequency close to the fabric limit of 500MHz, but without the significant dependency overheads typical of such processors.
|Original language||English (US)|
|Title of host publication||FPGA 2015 - 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays|
|Publisher||Association for Computing Machinery, Incacmhelp@acm.org|
|Number of pages||9|
|State||Published - Feb 22 2015|