On one step row readout technique of selector-less resistive arrays

Resistive crossbar arrays show significant improvement in terms of energy and area efficiency when compared to current SRAM based memory technologies. However, due to its resistive nature, it suffers from undesired current sneak-paths complicating read-out procedures. In this paper, we present a voltage-based reading technique in resistive memories. The simplicity of the readout circuit enables parallel reading where it is possible to read all the row data in the same cycle. Simulations results confirm the robustness of the technique, with wire resistance and variability of switching devices taken into consideration. Finally, a general figure of merit is introduced in order to compare the one step readout approach to other approaches.