On the impact of traffic statistics on quality of service for networks on chip

Stefano Santi; Bill Lin; Ljupco Kocarev; Gian Mario Maggio; Riccardo Rovatti; Gianluca Setti

doi:10.1109/ISCAS.2005.1465096

On the impact of traffic statistics on quality of service for networks on chip

Stefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. © 2005 IEEE.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Pages	2349-2352
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2005.1465096
State	Published - Dec 1 2005
Externally published	Yes

Access to Document

10.1109/ISCAS.2005.1465096

Cite this

@inproceedings{ff6d26284cb34ef7ad3602142bedfc4d,

title = "On the impact of traffic statistics on quality of service for networks on chip",

abstract = "Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. {\textcopyright} 2005 IEEE.",

author = "Stefano Santi and Bill Lin and Ljupco Kocarev and Maggio, {Gian Mario} and Riccardo Rovatti and Gianluca Setti",

note = "Generated from Scopus record by KAUST IRTS on 2023-02-15",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2005.1465096",

language = "English (US)",

pages = "2349--2352",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - On the impact of traffic statistics on quality of service for networks on chip

AU - Santi, Stefano

AU - Lin, Bill

AU - Kocarev, Ljupco

AU - Maggio, Gian Mario

AU - Rovatti, Riccardo

AU - Setti, Gianluca

N1 - Generated from Scopus record by KAUST IRTS on 2023-02-15

PY - 2005/12/1

Y1 - 2005/12/1

N2 - Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. © 2005 IEEE.

AB - Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. © 2005 IEEE.

UR - http://ieeexplore.ieee.org/document/1465096/

UR - http://www.scopus.com/inward/record.url?scp=37849021721&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1465096

DO - 10.1109/ISCAS.2005.1465096

M3 - Conference contribution

SP - 2349

EP - 2352

BT - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

On the impact of traffic statistics on quality of service for networks on chip

Abstract

Access to Document

Other files and links

Fingerprint

Cite this