@inproceedings{aa5bf53e6220495e9da9c4f930319dca,
title = "Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications",
abstract = "This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.",
keywords = "ANN, Junctionless Transistor, LTD, LTP, Neural Network, STP, Synaptic Transistor",
author = "{Raza Ansari}, {Md Hasan} and Nazek El-Atab",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023 ; Conference date: 07-03-2023 Through 10-03-2023",
year = "2023",
doi = "10.1109/EDTM55494.2023.10103084",
language = "English (US)",
series = "7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "7th IEEE Electron Devices Technology and Manufacturing Conference",
address = "United States",
}