TY - JOUR
T1 - Performance Limits and Potential of Multilayer Graphene–Tungsten Diselenide Heterostructures
AU - Yang, Shih-Hsien
AU - Yang, Feng-Shou
AU - Tang, Hao-Ling
AU - Chiu, Ming-Hui
AU - Lee, Ko-Chun
AU - Li, Mengjiao
AU - Lin, Che-Yi
AU - Li, Lain-Jong
AU - Tung, Vincent
AU - Xu, Yong
AU - Shi, Yumeng
AU - Lien, Chen-Hsin
AU - Lin, Yen-Fu
N1 - KAUST Repository Item: Exported on 2021-09-06
Acknowledgements: This work was supported by the Taiwan Ministry of Science and Technology (Grant No. MOST 108-2112-M-005-012-MY3 and 109-2112-M-005-013-MY3), and also supported in part by the National Natural Science Foundation of China under Grant No. 61974070 and 61874074, 1311 Talent Plan, and Start-Up Fund from Nanjing University of Posts and Telecommunications under Grant No. NY219003, and Shenzhen Peacock Plan (Grant No. KQTD2016053112042971).
PY - 2021/9/2
Y1 - 2021/9/2
N2 - Atomically thin tungsten diselenide (WSe2) transistors with multilayer graphene (w/ G) as contact electrodes are successfully fabricated by a precise area-controllable chemical vapor deposition method. The performance and electrical properties of the devices are explored. Compared to those of WSe2 transistors without graphene contacts (w/o G), the maximum current densities of the w/ G–WSe2 transistors increase by one to two orders of magnitude. In addition, the device performance is markedly improved for the w/ G–WSe2 transistors, including an on/off current ratio of ≈107, subthreshold swing of ≈150 mV/decade, and threshold voltage of ≈1.75 V. The improved performance of the w/ G–WSe2 transistors is ascribed to the alleviation of electrical contributions from metal–semiconductor contact resistance, which is consistent with the analysis of low-frequency noise measurements. In addition, self-trapping behavior in the WSe2 channel is found, which possibly paves a way to further optimize the performance of layered devices. Finally, an inverter using the w/ G–WSe2 transistors is demonstrated. These transistors represent a step forward in the development of layered graphene-based electronics suitable for energy-efficient and high-performance industrial-scale products.
AB - Atomically thin tungsten diselenide (WSe2) transistors with multilayer graphene (w/ G) as contact electrodes are successfully fabricated by a precise area-controllable chemical vapor deposition method. The performance and electrical properties of the devices are explored. Compared to those of WSe2 transistors without graphene contacts (w/o G), the maximum current densities of the w/ G–WSe2 transistors increase by one to two orders of magnitude. In addition, the device performance is markedly improved for the w/ G–WSe2 transistors, including an on/off current ratio of ≈107, subthreshold swing of ≈150 mV/decade, and threshold voltage of ≈1.75 V. The improved performance of the w/ G–WSe2 transistors is ascribed to the alleviation of electrical contributions from metal–semiconductor contact resistance, which is consistent with the analysis of low-frequency noise measurements. In addition, self-trapping behavior in the WSe2 channel is found, which possibly paves a way to further optimize the performance of layered devices. Finally, an inverter using the w/ G–WSe2 transistors is demonstrated. These transistors represent a step forward in the development of layered graphene-based electronics suitable for energy-efficient and high-performance industrial-scale products.
UR - http://hdl.handle.net/10754/670924
UR - https://onlinelibrary.wiley.com/doi/10.1002/aelm.202100355
U2 - 10.1002/aelm.202100355
DO - 10.1002/aelm.202100355
M3 - Article
SN - 2199-160X
SP - 2100355
JO - Advanced Electronic Materials
JF - Advanced Electronic Materials
ER -