Phase locked loop with fast tracking over wide stability range under grid faults

Ahmed S. Morsy; Prasad Enjeti; Shehab Ahmed; Ahmed Massoud

doi:10.1109/APEC.2014.6803468

Phase locked loop with fast tracking over wide stability range under grid faults

Ahmed S. Morsy, Prasad Enjeti, Shehab Ahmed, Ahmed Massoud

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations. © 2014 IEEE.

Original language	English (US)
Title of host publication	Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479923250
DOIs	https://doi.org/10.1109/APEC.2014.6803468
State	Published - Jan 1 2014
Externally published	Yes

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10.1109/APEC.2014.6803468

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title = "Phase locked loop with fast tracking over wide stability range under grid faults",

abstract = "This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations. {\textcopyright} 2014 IEEE.",

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Phase locked loop with fast tracking over wide stability range under grid faults. / Morsy, Ahmed S.; Enjeti, Prasad; Ahmed, Shehab et al.
Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC. Institute of Electrical and Electronics Engineers Inc., 2014.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Enjeti, Prasad

AU - Ahmed, Shehab

AU - Massoud, Ahmed

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-27

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations. © 2014 IEEE.

AB - This paper introduces a PLL characterized by fast dynamics, wide stability range and minimal deviations. The proposed PLL is based on a frequency adaptive filtering stage to minimize the frequency and phase deviations under unbalanced conditions and harmonic distortions. Furthermore, a simple mathematical formula is introduced to modify the conventional synchronous frame based PLL to provide more stabilization points for the PLL. The advantages of the proposed PLL are verified through simulations. © 2014 IEEE.

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M3 - Conference contribution

SN - 9781479923250

BT - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Phase locked loop with fast tracking over wide stability range under grid faults

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