TY - GEN
T1 - Power Efficient Image Processing with TMR Tunable Hybrid Approximate Adders
AU - Gulafshan, Gulafshan
AU - Kumar, Rajat
AU - Khan, Danial
AU - Amara, Selma
AU - Massoud, Yehia
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - An emerging spintronic device, magnetic tunnel junction (MTJ) mitigates the challenges like leakage power, high dynamic power as well as static power, faced by present CMOS technology. The non-volatility offers extra power saving during idle state by completely shut-down a MTJ based circuits without losing any data or extra hardware. Further, an approximate computing is a reliable technique for improving significant performance in trade of accuracy. In this paper, two fully non-volatile, 1-bit approximate adders are proposed with error distance in sum is two, extended to 12-bit hybrid adder in which a mix of approximate adders are placed on lower significant bits (LSB) and exact adder (EXA3) is placed on higher significant bits, and these hybrid adders are employed in image processing (implementing Gaussian filter) for removing noise. It is observed that the proposed adder (AXMFA1) is 23 % power efficient and reduces delay by 21 % by slightly compromising the accuracy (maximum error distance is 5) that implies the degradation in image quality: reduction of PSNR and SSIM by 0.13% and 0.28%.
AB - An emerging spintronic device, magnetic tunnel junction (MTJ) mitigates the challenges like leakage power, high dynamic power as well as static power, faced by present CMOS technology. The non-volatility offers extra power saving during idle state by completely shut-down a MTJ based circuits without losing any data or extra hardware. Further, an approximate computing is a reliable technique for improving significant performance in trade of accuracy. In this paper, two fully non-volatile, 1-bit approximate adders are proposed with error distance in sum is two, extended to 12-bit hybrid adder in which a mix of approximate adders are placed on lower significant bits (LSB) and exact adder (EXA3) is placed on higher significant bits, and these hybrid adders are employed in image processing (implementing Gaussian filter) for removing noise. It is observed that the proposed adder (AXMFA1) is 23 % power efficient and reduces delay by 21 % by slightly compromising the accuracy (maximum error distance is 5) that implies the degradation in image quality: reduction of PSNR and SSIM by 0.13% and 0.28%.
UR - http://www.scopus.com/inward/record.url?scp=85173600263&partnerID=8YFLogxK
U2 - 10.1109/NANO58406.2023.10231223
DO - 10.1109/NANO58406.2023.10231223
M3 - Conference contribution
AN - SCOPUS:85173600263
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 556
EP - 561
BT - 2023 IEEE 23rd International Conference on Nanotechnology, NANO 2023
PB - IEEE Computer Society
T2 - 23rd IEEE International Conference on Nanotechnology, NANO 2023
Y2 - 2 July 2023 through 5 July 2023
ER -