This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.
|Original language||English (US)|
|Title of host publication||2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Jan 8 2019|