Abstract
This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/μm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.
Original language | English (US) |
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Title of host publication | European Solid-State Device Research Conference |
Publisher | IEEE Computer Society |
Pages | 159-162 |
Number of pages | 4 |
ISBN (Electronic) | 8890084782 |
DOIs | |
State | Published - 2002 |
Externally published | Yes |
Event | 32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy Duration: Sep 24 2002 → Sep 26 2002 |
Other
Other | 32nd European Solid-State Device Research Conference, ESSDERC 2002 |
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Country/Territory | Italy |
City | Firenze |
Period | 09/24/02 → 09/26/02 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality