Scalable Complementary FeFET CAM Design

O. Bekdache; H. Nour Eddine; M. Al Tawil; R. Kanj; M. E. Fouda; Ahmed Eltawil

doi:10.1109/iscas46773.2023.10181788

Scalable Complementary FeFET CAM Design

O. Bekdache, H. Nour Eddine, M. Al Tawil, R. Kanj, M. E. Fouda, Ahmed Eltawil

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

CAMs are frequently employed for data-centric applications. They offer excellent parallelism. Traditionally, they were implemented using the area-consuming SRAM. Recent advancements suggest using compact nonvolatile memories (NVMs) to create CAM cells to reduce area. The ferroelectric field effect transistor (FeFET) has therefore emerged as an NVM device showing great potential in these memory architectures. In this work, we propose a novel multi-bit CAM architecture that utilizes p-type FeFETs – a topic yet to be explored in the literature – and we compare the latency, accuracy, and energy consumption of our design to other FeFET-based architectures demonstrating a 3-30× reduction in fail probability.

Original language	English (US)
Title of host publication	2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE
DOIs	https://doi.org/10.1109/iscas46773.2023.10181788
State	Published - Jul 21 2023

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10.1109/iscas46773.2023.10181788

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@inproceedings{78161ac7db944dfe9a33fa4e62c248b4,

title = "Scalable Complementary FeFET CAM Design",

abstract = "CAMs are frequently employed for data-centric applications. They offer excellent parallelism. Traditionally, they were implemented using the area-consuming SRAM. Recent advancements suggest using compact nonvolatile memories (NVMs) to create CAM cells to reduce area. The ferroelectric field effect transistor (FeFET) has therefore emerged as an NVM device showing great potential in these memory architectures. In this work, we propose a novel multi-bit CAM architecture that utilizes p-type FeFETs – a topic yet to be explored in the literature – and we compare the latency, accuracy, and energy consumption of our design to other FeFET-based architectures demonstrating a 3-30× reduction in fail probability.",

author = "O. Bekdache and Eddine, {H. Nour} and {Al Tawil}, M. and R. Kanj and Fouda, {M. E.} and Ahmed Eltawil",

note = "KAUST Repository Item: Exported on 2023-07-25",

year = "2023",

month = jul,

day = "21",

doi = "10.1109/iscas46773.2023.10181788",

language = "English (US)",

booktitle = "2023 IEEE International Symposium on Circuits and Systems (ISCAS)",

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TY - GEN

T1 - Scalable Complementary FeFET CAM Design

AU - Bekdache, O.

AU - Eddine, H. Nour

AU - Al Tawil, M.

AU - Kanj, R.

AU - Fouda, M. E.

AU - Eltawil, Ahmed

N1 - KAUST Repository Item: Exported on 2023-07-25

PY - 2023/7/21

Y1 - 2023/7/21

N2 - CAMs are frequently employed for data-centric applications. They offer excellent parallelism. Traditionally, they were implemented using the area-consuming SRAM. Recent advancements suggest using compact nonvolatile memories (NVMs) to create CAM cells to reduce area. The ferroelectric field effect transistor (FeFET) has therefore emerged as an NVM device showing great potential in these memory architectures. In this work, we propose a novel multi-bit CAM architecture that utilizes p-type FeFETs – a topic yet to be explored in the literature – and we compare the latency, accuracy, and energy consumption of our design to other FeFET-based architectures demonstrating a 3-30× reduction in fail probability.

AB - CAMs are frequently employed for data-centric applications. They offer excellent parallelism. Traditionally, they were implemented using the area-consuming SRAM. Recent advancements suggest using compact nonvolatile memories (NVMs) to create CAM cells to reduce area. The ferroelectric field effect transistor (FeFET) has therefore emerged as an NVM device showing great potential in these memory architectures. In this work, we propose a novel multi-bit CAM architecture that utilizes p-type FeFETs – a topic yet to be explored in the literature – and we compare the latency, accuracy, and energy consumption of our design to other FeFET-based architectures demonstrating a 3-30× reduction in fail probability.

UR - http://hdl.handle.net/10754/693200

UR - https://ieeexplore.ieee.org/document/10181788/

U2 - 10.1109/iscas46773.2023.10181788

DO - 10.1109/iscas46773.2023.10181788

M3 - Conference contribution

BT - 2023 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

ER -

Scalable Complementary FeFET CAM Design

Abstract

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