Surface preparation techniques used for fabricating high-k/metal gate device structures

As transistor sizes continue to shrink, the gate dielectric's equivalent oxide thickness (EOT) must scale below 1.0 nm to increase the gate stack capacitance density. Conventional SiO_xN_y gate dielectrics will eventually need to be replaced by higher dielectric constant materials, and the polysilicon gate depletion will become a significant part of the total T_inv, necessitating the use of metal gate electrodes to achieve thinner capacitance equivalent thickness (CET). Although implementation of the high-κ and/or the metal gate electrode will be delayed until 2008 [1], the introduction of high-K dielectrics and metal gate electrodes into the manufacturing processes is nevertheless believed to be forthcoming. Integrating these new gate stack materials (high-κ and metal gates) into the manufacturing process flow will be complex inasmuch as they do not behave like the materials that the industry has used for the past 30 years. This will especially affect the various wet clean steps associated with device fabrication: (1) surface preparation before high-κ deposition, (2) metal wet etch as part of the CMOS dual metal gate fabrication process, and (3) complete removal of the high-κ dielectric over the source/drain (S/D) areas after gate definition. This paper will review the surface preparation techniques associated with these three significant processes for the high-κ/metal gate stack fabrication process.