System redundancy; A means of improving process variation yield degradation in memory arrays

Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/VDAT.2006.258144

System redundancy; A means of improving process variation yield degradation in memory arrays

Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

This paper addresses the fact that memory yield will be the dominant issue affecting overall yield in nano-seale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics. ©2006 IEEE.

Original language	English (US)
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2006.258144
State	Published - Oct 1 2007
Externally published	Yes

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10.1109/VDAT.2006.258144

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title = "System redundancy; A means of improving process variation yield degradation in memory arrays",

abstract = "This paper addresses the fact that memory yield will be the dominant issue affecting overall yield in nano-seale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics. {\textcopyright}2006 IEEE.",

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N2 - This paper addresses the fact that memory yield will be the dominant issue affecting overall yield in nano-seale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics. ©2006 IEEE.

AB - This paper addresses the fact that memory yield will be the dominant issue affecting overall yield in nano-seale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics. ©2006 IEEE.

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BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

ER -

System redundancy; A means of improving process variation yield degradation in memory arrays

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