Task allocation of safety-critical applications on reconfigurable multi-core architectures

Tom Guillaumet; Eric Feron; Philippe Baufreton; François Neumann; Kavitha Madhu; Madhava Krishna; S. K. Nandy; Ranjani Narayan; Chandan Haldar

doi:10.1109/DASC.2017.8101992

Task allocation of safety-critical applications on reconfigurable multi-core architectures

Tom Guillaumet, Eric Feron, Philippe Baufreton, François Neumann, Kavitha Madhu, Madhava Krishna, S. K. Nandy, Ranjani Narayan, Chandan Haldar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

With the onset of multi-core chips, the single-core market is closing down. Developing avionics systems hosted on multi-core chips that enforce safety-criticality constraints constitutes a challenge for the aerospace industry. This paper presents a reconfigurable multi-core architecture and studies its suitability for hosting safety-critical embedded applications. A task allocation algorithm for this specific architecture is proposed, and the last section demonstrates its behavior and analyzes its efficiency.

Original language	English (US)
Title of host publication	AIAA/IEEE Digital Avionics Systems Conference - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781538603659
DOIs	https://doi.org/10.1109/DASC.2017.8101992
State	Published - Nov 8 2017
Externally published	Yes

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10.1109/DASC.2017.8101992

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Guillaumet, T., Feron, E., Baufreton, P., Neumann, F., Madhu, K., Krishna, M., Nandy, S. K., Narayan, R., & Haldar, C. (2017). Task allocation of safety-critical applications on reconfigurable multi-core architectures. In AIAA/IEEE Digital Avionics Systems Conference - Proceedings Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DASC.2017.8101992

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AU - Guillaumet, Tom

AU - Feron, Eric

AU - Baufreton, Philippe

AU - Neumann, François

AU - Madhu, Kavitha

AU - Krishna, Madhava

AU - Nandy, S. K.

AU - Narayan, Ranjani

AU - Haldar, Chandan

N1 - Generated from Scopus record by KAUST IRTS on 2021-02-18

PY - 2017/11/8

Y1 - 2017/11/8

N2 - With the onset of multi-core chips, the single-core market is closing down. Developing avionics systems hosted on multi-core chips that enforce safety-criticality constraints constitutes a challenge for the aerospace industry. This paper presents a reconfigurable multi-core architecture and studies its suitability for hosting safety-critical embedded applications. A task allocation algorithm for this specific architecture is proposed, and the last section demonstrates its behavior and analyzes its efficiency.

AB - With the onset of multi-core chips, the single-core market is closing down. Developing avionics systems hosted on multi-core chips that enforce safety-criticality constraints constitutes a challenge for the aerospace industry. This paper presents a reconfigurable multi-core architecture and studies its suitability for hosting safety-critical embedded applications. A task allocation algorithm for this specific architecture is proposed, and the last section demonstrates its behavior and analyzes its efficiency.

UR - http://ieeexplore.ieee.org/document/8101992/

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U2 - 10.1109/DASC.2017.8101992

DO - 10.1109/DASC.2017.8101992

M3 - Conference contribution

SN - 9781538603659

BT - AIAA/IEEE Digital Avionics Systems Conference - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Task allocation of safety-critical applications on reconfigurable multi-core architectures

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