Abstract
This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (Vt) control of incorporating La and Al into HKMG devices. A dipole moment model explaining Vt tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La2O3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable Vt for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO2/Si interface on the HKMG MOSFET Vt-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.
Original language | English (US) |
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Pages (from-to) | 1722-1727 |
Number of pages | 6 |
Journal | Microelectronic Engineering |
Volume | 86 |
Issue number | 7-9 |
DOIs | |
State | Published - Jul 2009 |
Externally published | Yes |
Keywords
- CMOS
- Capping layer
- EOT
- High-k
- Metal gate
- Threshold voltage control
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering