TY - GEN
T1 - Tin (Sn) for enhancing performance in silicon CMOS
AU - Hussain, Aftab M.
AU - Fahad, Hossain M.
AU - Singh, Nirpendra
AU - Sevilla, Galo T.
AU - Schwingenschlögl, Udo
AU - Hussain, Muhammad Mustafa
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2013/10
Y1 - 2013/10
N2 - We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
AB - We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
UR - http://hdl.handle.net/10754/564809
UR - http://ieeexplore.ieee.org/document/6707470/
UR - http://www.scopus.com/inward/record.url?scp=84893767635&partnerID=8YFLogxK
U2 - 10.1109/NMDC.2013.6707470
DO - 10.1109/NMDC.2013.6707470
M3 - Conference contribution
SN - 9781479933877
SP - 13
EP - 15
BT - 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -