Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform

Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell

Research output: Contribution to journalArticlepeer-review

38 Scopus citations


Emerging hybrid reconfigurable platforms tightly couple capable processors with high performance reconfigurable fabrics. This promises to move the focus of reconfigurable computing systems from static accelerators to a more software oriented view, where reconfiguration is a key enabler for exploiting the available resources. This requires a revised look at how to manage the execution of such hardware tasks within a processor-based system, and in doing so, how to virtualize the resources to ensure isolation and predictability. This view is further supported by trends towards amalgamation of computation in the automotive and avionics domains, where such properties are essential to overall system reliability. We present the virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). The CODEZERO hypervisor has been modified to leverage the capabilities of the FPGA fabric, with support for discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric. We characterise the communication overheads in such a hybrid system to motivate the importance of lean management, before quantifying the context switch overhead of the hypervisor approach. We then compare the resulting idle time for a standard Linux implementation and the proposed hypervisor method, showing two orders of magnitude improved performance with the hypervisor.
Original languageEnglish (US)
Pages (from-to)61-76
Number of pages16
JournalJournal of Signal Processing Systems
Issue number1-2
StatePublished - Oct 1 2014
Externally publishedYes


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