VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Raja Arslan Naseer; Muneeba Nasim; Muhummad Sohaib; Ch Jabbar Younis; Anzar Mehmood; Mehboob Alam; Yehia Mahmoud Massoud

doi:10.1016/j.vlsi.2022.07.009

VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Raja Arslan Naseer, Muneeba Nasim, Muhummad Sohaib, Ch Jabbar Younis, Anzar Mehmood, Mehboob Alam, Yehia Mahmoud Massoud

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.

Original language	English (US)
Pages (from-to)	253-259
Number of pages	7
Journal	Integration
Volume	87
DOIs	https://doi.org/10.1016/j.vlsi.2022.07.009
State	Published - Aug 18 2022

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1016/j.vlsi.2022.07.009

https://repository.kaust.edu.sa/bitstream/10754/680842/1/VLSI%20Integration.pdf

Cite this

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title = "VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform",

abstract = "Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.",

author = "Naseer, {Raja Arslan} and Muneeba Nasim and Muhummad Sohaib and Younis, {Ch Jabbar} and Anzar Mehmood and Mehboob Alam and Massoud, {Yehia Mahmoud}",

note = "KAUST Repository Item: Exported on 2022-09-09 Acknowledgements: The authors extend their appreciation to the Mirpur University of Science and Technology (MUST), University of Poonch Rawalakot and Innovative Technologies Laboratories (ITL), King Abdullah University of Science and Technology for supporting this research.",

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doi = "10.1016/j.vlsi.2022.07.009",

language = "English (US)",

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journal = "Integration",

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T1 - VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

AU - Naseer, Raja Arslan

AU - Nasim, Muneeba

AU - Sohaib, Muhummad

AU - Younis, Ch Jabbar

AU - Mehmood, Anzar

AU - Alam, Mehboob

AU - Massoud, Yehia Mahmoud

N1 - KAUST Repository Item: Exported on 2022-09-09 Acknowledgements: The authors extend their appreciation to the Mirpur University of Science and Technology (MUST), University of Poonch Rawalakot and Innovative Technologies Laboratories (ITL), King Abdullah University of Science and Technology for supporting this research.

PY - 2022/8/18

Y1 - 2022/8/18

N2 - Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.

AB - Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.

UR - http://hdl.handle.net/10754/680842

UR - https://linkinghub.elsevier.com/retrieve/pii/S0167926022000943

UR - http://www.scopus.com/inward/record.url?scp=85136210601&partnerID=8YFLogxK

U2 - 10.1016/j.vlsi.2022.07.009

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VL - 87

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EP - 259

JO - Integration

JF - Integration

ER -

VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Abstract

ASJC Scopus subject areas

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