TY - GEN
T1 - Work-in-progress: Eficient pulsed-latch implementation for multiport register files
AU - Elsharkasy, Wael M.
AU - Yantir, Hasan Erdem
AU - Khajeh, Amin
AU - Eltawil, Ahmed M.
AU - Kurdahi, Fadi J.
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2017/10/15
Y1 - 2017/10/15
N2 - In this paper, register file design using pulsed latches is presented. Having some advantages in performance, area and power, pulsed latches represent an attractive implementation of register files. In addition, a proposed multiport register file architecture is introduced using single physical read/write ports to virtualize additional ports for read and write. The initial results show huge savings in area and power in comparison to the traditional architectures.
AB - In this paper, register file design using pulsed latches is presented. Having some advantages in performance, area and power, pulsed latches represent an attractive implementation of register files. In addition, a proposed multiport register file architecture is introduced using single physical read/write ports to virtualize additional ports for read and write. The initial results show huge savings in area and power in comparison to the traditional architectures.
UR - http://dl.acm.org/citation.cfm?doid=3125501.3125515
UR - http://www.scopus.com/inward/record.url?scp=85035325890&partnerID=8YFLogxK
U2 - 10.1145/3125501.3125515
DO - 10.1145/3125501.3125515
M3 - Conference contribution
SN - 9781450351843
BT - Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017
PB - Association for Computing Machinery, [email protected]
ER -