Hardware Realization of Chaos Based Symmetric Image Encryption

  • Mohamed L. Barakat

Student thesis: Master's Thesis


This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.
Date of AwardJun 2012
Original languageEnglish (US)
Awarding Institution
  • Computer, Electrical and Mathematical Sciences and Engineering
SupervisorKhaled Salama (Supervisor)


  • Chaos
  • FPGA
  • NIST
  • Post-Processing
  • Black and stream ciphers
  • Image encryption

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